A 12/16 GSps Time-Interleaved Pipelined-SAR ADC with Temperature Robust Performance at 0.75V Supply in 7nm FinFET Technology-Reference-Cited by-同舟云学术

A 12/16 GSps Time-Interleaved Pipelined-SAR ADC with Temperature Robust Performance at 0.75V Supply in 7nm FinFET Technology

Published:2023-09-11 Issue: Volume: Page:
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Container-title:ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC)
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Author:

Palm Mattias¹,Mastantuono Daniele¹,Jansson Christer¹,Backenius Erik¹,Ivanisevic Nikola¹,Normark Mikael¹,Harikumar Prakash¹,Yee My Chien¹,Leidenhed Andreas¹,Strandberg Roland¹,Sharma Sunny¹,Ghaedrahmati Hanie¹,Anderson Martin¹,Nygren Peter¹,Sjögren Peter¹,Säll Erik¹,Hägglund Robert¹,Sundström Lars¹

Affiliation:

1. Ericsson AB,Sweden

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10268677/10268683/10268755.pdf?arnumber=10268755

Reference6 articles.

1. A 12-bit 10GS/s 16-Channel Time-Interleaved ADC with a Digital Processing Timing-Skew Background Calibration in 5nm FinFET

2. A Temperature Compensation Technique for a Dynamic Amplifier in Pipelined-SAR ADCs

3. A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology

4. A 5-GS/s 158.6-mW 9.4-ENOB PassiveSampling Time-Interleaved Three-Stage Pipelined-SAR ADC With Analog--Digital Corrections in 28-nm CMOS;ramkaj;IEEE J Solid-State Circuits,2020

5. A 12-b 18-GS/s RF Sampling ADC With an Integrated Wideband Track-and-Hold Amplifier and Background Calibration

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