3.3 A 5GS/s 158.6mW 12b Passive-Sampling 8×-Interleaved Hybrid ADC with 9.4 ENOB and 160.5dB FoM<inf>S</inf> in 28nm CMOS-Reference-Cited by-同舟云学术

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3.3 A 5GS/s 158.6mW 12b Passive-Sampling 8×-Interleaved Hybrid ADC with 9.4 ENOB and 160.5dB FoMS in 28nm CMOS

Published:2019-02 Issue: Volume: Page:
ISSN:
Container-title:2019 IEEE International Solid- State Circuits Conference - (ISSCC)
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Author:

Ramkaj Athanasios,Ramos Juan Carlos Pena,Lyu Yifan,Strackx Maarten,Marcel Pelgrom J. M.,Steyaert Michiel,Verhelst Marian,Tavernier Filip

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8656625/8662285/08662490.pdf?arnumber=8662490

Cited by 24 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 2-GS/s Time-Interleaved ADC With Embedded Background Calibrations and a Novel Reference Buffer for Reduced Inter-Channel Crosstalk;IEEE Journal of Solid-State Circuits;2024

2. A Single-Channel 12-b 2-GS/s PVT-Robust Pipelined ADC With Sturdy Ring Amplifier and Time-Domain Quantizer;IEEE Journal of Solid-State Circuits;2024

3. Methods to Improve Linearity of Signal’s Analog-to-Digital Conversion with Self-Calibration;Machine Learning-based Design and Optimization of High-Speed Circuits;2023-12-31

4. A 4.8 GS/s 11b Time-Interleaved TDC-Assisted SAR ADC with High-Speed Latch-based VTC;ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC);2023-09-11

5. A 9-Bit 500-ms/s 4-Stage Pipelined SAR ADC With Wide Input Common-Mode Range Using Replica-Biased Dynamic Residue Amplifiers;IEEE Access;2023

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