A 1-GS/s 8-Bit 12.01-fJ/conv.-step Two-Step SAR ADC in 28-nm FDSOI Technology
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8011414/8871355/08877963.pdf?arnumber=8877963
Cited by 9 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A 4.8 GS/s 11b Time-Interleaved TDC-Assisted SAR ADC with High-Speed Latch-based VTC;ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC);2023-09-11
2. A 1.38-mW 7-bit 1.7-GS/s Single-Channel Loop-Unrolled SAR ADC in 22-nm FD-SOI With 8.85 fJ/Conv.-Step for GHz Mobile Communication and Radar Systems;IEEE Transactions on Microwave Theory and Techniques;2023-09
3. A Low Power High-Speed 12-Bit SAR ADC using Split Capacitor Based DAC at 45 nm CMOS Technology;2022 IEEE 2nd Mysore Sub Section International Conference (MysuruCon);2022-10-16
4. High-Efficiency Data Conversion Interface for Reconfigurable Function-in-Memory Computing;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2022-09
5. A 7-Bit Two-Step Flash ADC With Sample-and-Hold Sharing Technique;IEEE Journal of Solid-State Circuits;2022-09
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