A 1.2-GS/s 8-bit Two-Step SAR ADC in 65-nm CMOS With Passive Residue Transfer-Reference-Cited by-同舟云学术

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A 1.2-GS/s 8-bit Two-Step SAR ADC in 65-nm CMOS With Passive Residue Transfer

Published:2017-06 Issue:6 Volume:52 Page:1551-1562
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Huang Hai^ORCID,Du Ling,Chiu Yun

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/7933283/07894168.pdf?arnumber=7894168

Cited by 24 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. CoMN: Algorithm-Hardware Co-Design Platform for Nonvolatile Memory-Based Convolutional Neural Network Accelerators;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-07

2. A 12-bit 1.5-GS/s Single-Channel Pipelined SAR ADC With a Pipelined Residue Amplification Stage;IEEE Journal of Solid-State Circuits;2024

3. An 8-bit 1.5-GS/s Voltage–Time Hybrid Two-Step ADC With Cross-Coupled Linearized VTC;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-12

4. A 2.28mW 100 MS/s 10-bit ping-pong configuration SAR-assisted pipeline ADC;Analog Integrated Circuits and Signal Processing;2023-11-16

5. An 8-bit 1.5-GS/s Two-Step SAR ADC With Embedded Interstage Gain;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-11

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