A 0.55-mm2 8-bit 32-GS/s TI-SAR ADC with optimized hierarchical sampling architecture
Author:
Funder
Scientific Research Plan Projects of Shaanxi Education Department
Fundamental Research Funds for the Central Universities
National Natural Science Foundation of China
Publisher
Elsevier BV
Reference20 articles.
1. A 56-GS/s 8-bit time-interleaved ADC with ENOB and BW enhancement techniques in 28-nm CMOS;Sun;IEEE J. Solid State Circ.,2019
2. Analysis and design of a high-bandwidth front-end sampler for time-interleaved ADCs;Ding;Circ. Syst. Signal Process.,2022
3. Radio frequency analog-to-digital converters: systems and circuits review;Li;Microelectron. J.,2022
4. Design considerations for interleaved ADCs;Razavi;IEEE J. Solid State Circ.,2013
5. A 15.1-mW 6-GS/s 6-bit single-channel flash ADC with selectively activated 8× time-domain latch interpolation;Yi;IEEE J. Solid State Circ.,2021
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