An evenly-spaced-phase all-digital DLL using dual-loop SAR control
Author:
Funder
Fundamental Research Funds for the Central Universities
National Natural Science Foundation of China
Publisher
Elsevier BV
Reference28 articles.
1. High time-resolution readout integrated circuit using DLL for portable cosmic ray muon detection;Chen;IEEE Trans. Nucl. Sci.,2021
2. A 2.4-GHz 1.5-mW digital multiplying delay-locked loop using pulsewidth comparator and double injection technique;Kim;IEEE J. Solid-State Circuits,2017
3. A low-reference spur MDLL-based clock multiplier and derivation of discrete-time noise transfer function for phase noise analysis;Tak;IEEE Trans. Circuits Syst. Regul. Pap.,2018
4. A fast-locking all-digital multiplying DLL for fractional-ratio dynamic frequency scaling;Kim;IEEE Trans. Circuits Syst. Express Briefs,2018
5. A 1.12–1.91 mW/GHz 2.46–4.92 GHz cascaded clock multiplier in 65 nm CMOS;Gautam;IEEE J. Solid-State Circuits,2022
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