A Column-Parallel Time-Interleaved SAR/SS ADC for Computing in Memory with 2-8bit Reconfigurable Resolution
Author:
Affiliation:
1. Nanjing University,Nanjing,China
Funder
Research and Development
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10168547/10168548/10168604.pdf?arnumber=10168604
Reference32 articles.
1. ADC trends and impact on SAR ADC architecture and analysis
2. 11-bit Column-Parallel Single-Slope ADC With First-Step Half-Reference Ramping Scheme for High-Speed CMOS Image Sensors
3. An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC
4. Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques
5. Tiny ci-SAR A/D Converter for Deep Neural Networks in Analog in-Memory Computation
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1. A Compact and Low-Power Column Readout Circuit based on Digital Delay Chain;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
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