Author:
Fredenburg Jeffrey,Flynn Michael P.
Cited by
6 articles.
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1. A low-power 8-bit 1-MS/s single-ended SAR ADC in 130-nm CMOS for medical devices;Journal of Electrical Systems and Information Technology;2024-06-12
2. A Column-Parallel Time-Interleaved SAR/SS ADC for Computing in Memory with 2-8bit Reconfigurable Resolution;2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS);2023-06-11
3. Unlimited Sampling Radar: Life Below the Quantization Noise;ICASSP 2023 - 2023 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP);2023-06-04
4. Joint background calibration of gain and timing mismatch errors with low hardware cost for time‐interleaved ADCs;IET Circuits, Devices & Systems;2019-02-15
5. Design of a low power 10-bit 12MS/s asynchronous SAR ADC in 65nm CMOS;Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design - SBCCI '19;2019