A Compact and Low-Power Column Readout Circuit based on Digital Delay Chain
Author:
Affiliation:
1. Korea Advanced Institute of Science and Technology (KAIST),School of Electrical Engineering,Daejeon,Republic of Korea
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10557746/10557828/10558326.pdf?arnumber=10558326
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1. ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars
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3. A 40-nm, 64-Kb, 56.67 TOPS/W Voltage-Sensing Computing-In-Memory/Digital RRAM Macro Supporting Iterative Write With Verification and Online Read-Disturb Detection
4. 16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips
5. A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS
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