32.5 A 24GHz Self-Calibrated ADPLL-Based FMCW Synthesizer with 0.01% rms Frequency Error Under 3.2GHz Chirp Bandwidth and 320MHz/μs Slope
Author:
Funder
National Natural Science Foundation of China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9365732/9365735/09365949.pdf?arnumber=9365949
Cited by 19 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A 74GHz-80GHz 1.2GHz/μs-Slope 20.9mW FMCW Synthesizer with TDC-Gain-Independent Loop-Bandwidth Employing a TDC-Offset- Free Type-II Digital PLL and a Linearized Hybrid-Tuning DCO;2024 IEEE Radio Frequency Integrated Circuits Symposium (RFIC);2024-06-16
2. A 4.25GHz-8.45GHz 67%-Chirp-Fractional-Bandwidth -121.5dBc/Hz-PN@1MHz 88fs-Jitter FMCW Synthesizer with Bandwidth-Boosting and Phase-Noise-Cancellation Techniques;2024 IEEE Radio Frequency Integrated Circuits Symposium (RFIC);2024-06-16
3. 32.6 A 76-to-81GHz Direct-Digital 7b 14GS/s Double-Balanced I/Q Mixing-DAC Radar-Waveform Synthesizer;2024 IEEE International Solid-State Circuits Conference (ISSCC);2024-02-18
4. 10.6 A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion;2024 IEEE International Solid-State Circuits Conference (ISSCC);2024-02-18
5. 10.7 An 11GHz 2nd-order DPD FMCW Chirp Generator with 0.051% rms Frequency Error under a 2.3GHz Chirp Bandwidth, 2.3GHz/μs Slope, and 50ns Idle Time in 65nm CMOS;2024 IEEE International Solid-State Circuits Conference (ISSCC);2024-02-18
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