A 74GHz-80GHz 1.2GHz/μs-Slope 20.9mW FMCW Synthesizer with TDC-Gain-Independent Loop-Bandwidth Employing a TDC-Offset- Free Type-II Digital PLL and a Linearized Hybrid-Tuning DCO

Author:

Liu Yi1,Jing Zixi1,Liu Zhiyu1,Yip Chi C.1,Zong Zhirui2,Luong Howard C.1

Affiliation:

1. Hong Kong University of Science and Technology,China

2. Hong Kong University of Science and Technology,Guangzhou,China

Publisher

IEEE

Reference6 articles.

1. A 23GHz Low-Phase-Noise Digital Bang-Bang PLL for Fast Triangular and Saw-Tooth Chirp Modulation;Cherniak;ISSCC,2018

2. A Self-Adapted Two-Point Modulation Type-II Digital PLL for Fast Chirp Rate and Wide Chirp-Bandwidth FMCW Signal Generator;Deng;JSSC,2022

3. 32.5 A 24GHz Self-Calibrated ADPLL-Based FMCW Synthesizer with 0.01% rms Frequency Error Under 3.2GHz Chirp Bandwidth and 320MHz/μs Slope

4. A 16GHz, 41kHzrms Frequency Error, Background-Calibrated, Duty-Cycled FMCW Charge-Pump PLL;Renukaswamy;ISSCC,2023

5. Design Methodology for Phase-Locked Loops Using Binary (Bang-Bang) Phase Detectors

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