10.7 An 11GHz 2nd-order DPD FMCW Chirp Generator with 0.051% rms Frequency Error under a 2.3GHz Chirp Bandwidth, 2.3GHz/μs Slope, and 50ns Idle Time in 65nm CMOS-Reference-Cited by-同舟云学术

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10.7 An 11GHz 2nd-order DPD FMCW Chirp Generator with 0.051% rms Frequency Error under a 2.3GHz Chirp Bandwidth, 2.3GHz/μs Slope, and 50ns Idle Time in 65nm CMOS

Published:2024-02-18 Issue: Volume: Page:200-202
ISSN:
Container-title:2024 IEEE International Solid-State Circuits Conference (ISSCC)
language:
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Author:

Wang Xuan¹,Ma Xujun²,Fu Yupeng¹,Zhou Yuqian¹,Li Ang¹,Yang Shuo¹,Wu Xu¹,Wang Dongming¹,Li Lianming¹,You Xiaohu¹

Affiliation:

1. Southeast University,Nanjing,China

2. Télécom SudParis,Paris,France

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10454133/10454267/10454283.pdf?arnumber=10454283

Reference8 articles.

1. 32.5 A 24GHz Self-Calibrated ADPLL-Based FMCW Synthesizer with 0.01% rms Frequency Error Under 3.2GHz Chirp Bandwidth and 320MHz/μs Slope

2. 17.7 A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/µs Slope and 1.2GHz Chirp Bandwidth

3. A Self-Calibrated 16GHz Subsampling-PLL-Based 30 Fast Chirp FMCW Modulator with 1.5GHz Bandwidth and 100kHz rms Error;Shi;ISSCC,2019

4. A 23-GHz Low-Phase-Noise Digital Bang–Bang PLL for Fast Triangular and Sawtooth Chirp Modulation

5. An 11.4-to-16.4GHz FMCW Digital PLL with Cycle-slipping Compensation and Back-tracking DPD Achieving 0.034% RMS Frequency Error under 3.4-GHz Chirp Bandwidth and 960-MHz/μs Chirp Slope

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