A 0.82mW 14b 130MS/S Pipelined-SAR ADC With a Distributed Averaging Correlated Level Shifting (DACLS) Ringamp and Bypass-Window Backend
Author:
Affiliation:
1. National Cheng Kung University,Tainan,Taiwan
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9731529/9731102/09731546.pdf?arnumber=9731546
Reference5 articles.
1. A 75.3-dB SNDR 24-MS/s Ring Amplifier-Based Pipelined ADC Using Averaging Correlated Level Shifting and Reference Swapping for Reducing Errors From Finite Opamp Gain and Capacitor Mismatch
2. An Over-60 dB True Rail-to-Rail Performance Using Correlated Level Shifting and an Opamp With Only 30 dB Loop Gain
3. A 0.85 fJ/conversion-step 10b 200 kS/s subranging SAR ADC in 40 nm CMOS;tai;ISSCC,2014
4. 16.4 A Calibration-Free 71.7dB SNDR 100MS/s 0.7mW Weighted-Averaging Correlated Level Shifting Pipelined SAR ADC with Speed-Enhancement Scheme
5. A 10.0 ENOB, 6.2 fJ/conv.-step, 500 MS/s Ringamp-Based Pipelined-SAR ADC with Background Calibration and Dynamic Reference Regulation in 16nm CMOS
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