9.4 A 182.3dB FoM<sub>s</sub> 50MS/s Pipelined-SAR ADC using Cascode Capacitively Degenerated Dynamic Amplifier and MSB Pre-Conversion Technique-Reference-Cited by-同舟云学术

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9.4 A 182.3dB FoM_s 50MS/s Pipelined-SAR ADC using Cascode Capacitively Degenerated Dynamic Amplifier and MSB Pre-Conversion Technique

Published:2024-02-18 Issue: Volume: Page:174-176
ISSN:
Container-title:2024 IEEE International Solid-State Circuits Conference (ISSCC)
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Author:

Chen Zhuoyi¹,Shen Linxiao¹,Ye Siyuan¹,Gao Jihang¹,Li Jie¹,Cui Jiajia¹,Xu Xinhang¹,Luan Yaohui¹,Zhang Hao²,Ye Le¹,Huang Ru¹

Affiliation:

1. Peking University,Beijing,China

2. Nano Core Chip Electronic Technology,Hangzhou,China

Funder

National Natural Science Foundation of China

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10454133/10454267/10454297.pdf?arnumber=10454297

Reference6 articles.

1. A 0.82mW 14b 130MS/S Pipelined-SAR ADC With a Distributed Averaging Correlated Level Shifting (DACLS) Ringamp and Bypass-Window Backend

2. 27.4 A 0.4-to-40MS/s 75.7dB-SNDR Fully Dynamic Event-Driven Pipelined ADC with 3-Stage Cascoded Floating Inverter Amplifier

3. A 65-dB-SNDR Pipelined SAR ADC Using PVT-Robust Capacitively Degenerated Dynamic Amplifier

4. A 79.5dB-SNDR Pipelined-SAR ADC with a Linearity-Shifting 32× Dynamic Amplifier and Mounted-Over-Die Bypass Capacitors

5. A Capacitively Degenerated 100-dB Linear 20–150 MS/s Dynamic Amplifier

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