27.4 A 0.4-to-40MS/s 75.7dB-SNDR Fully Dynamic Event-Driven Pipelined ADC with 3-Stage Cascoded Floating Inverter Amplifier-Reference-Cited by-同舟云学术

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27.4 A 0.4-to-40MS/s 75.7dB-SNDR Fully Dynamic Event-Driven Pipelined ADC with 3-Stage Cascoded Floating Inverter Amplifier

Published:2021-02-13 Issue: Volume: Page:
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Container-title:2021 IEEE International Solid- State Circuits Conference (ISSCC)
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Author:

Tang Xiyuan,Yang Xiangxing,Liu Jiaxin,Shi Wei,Pan David Z.,Sun Nan

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9365732/9365735/09365753.pdf?arnumber=9365753

Cited by 42 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Partially Feedback NSSAR Embedded Third-Order Delta–Sigma Modulator With Gain-Boosted Two-Stage FIAs;IEEE Journal of Solid-State Circuits;2024-09

2. Analysis of Stability, Noise, and Design Guidelines for a Cascaded Floating-Inverter Amplifier;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-09

3. A Floating-Ring Hybrid Amplifier Insensitive to PVT and Common-mode Variation without CMFB for High-Speed ADCs;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

4. A PVT-Robust Open-loop Gm-Ratio ×16 Gain Residue Amplifier for >1 GS/s Pipelined ADCs;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

5. A Delta-Sigma-Based Computing-In-Memory Macro Targeting Edge Computation;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

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