A Floating-Ring Hybrid Amplifier Insensitive to PVT and Common-mode Variation without CMFB for High-Speed ADCs
Author:
Affiliation:
1. Tsinghua University,School of Integrated Circuits,Beijing,China,100084
2. Beijing Smart-Chip Microelectronics Technology Co., Ltd.,Beijing,China,100084
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10557746/10557828/10558189.pdf?arnumber=10558189
Reference8 articles.
1. A 10.0 ENOB, 6.2 fJ/conv.-step, 500 MS/s Ringamp-Based Pipelined-SAR ADC with Background Calibration and Dynamic Reference Regulation in 16nm CMOS
2. A 4-GS/s 10-ENOB 75-mW Ringamp ADC in 16-nm CMOS With Background Monitoring of Distortion
3. A 0.004mm2 200MS/S Pipelined SAR ADC with kT/C Noise Cancellation and Robust Ring-Amp
4. 27.4 A 0.4-to-40MS/s 75.7dB-SNDR Fully Dynamic Event-Driven Pipelined ADC with 3-Stage Cascoded Floating Inverter Amplifier
5. Analysis and Design of a Discrete-Time Delta-Sigma Modulator Using a Cascoded Floating-Inverter-Based Dynamic Amplifier
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