A 10.0 ENOB, 6.2 fJ/conv.-step, 500 MS/s Ringamp-Based Pipelined-SAR ADC with Background Calibration and Dynamic Reference Regulation in 16nm CMOS
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx7/9492225/9492226/09492354.pdf?arnumber=9492354
Cited by 13 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A 10b 700 MS/s Single-Channel 1b/Cycle SAR ADC Using a Monotonic-Specific Feedback SAR Logic With Power-Delay-Optimized Unbalanced N/P-MOS Sizing;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-12
2. A calibration-free 10.7 fJ/conv.-step 12-bit 120-MS/s pipelined SAR ADC in 40nm CMOS;Journal of Physics: Conference Series;2023-10-01
3. A 13b 600-675MS/s Tri-State Pipelined-SAR ADC With Inverter-Based Open-Loop Residue Amplifier;IEEE Journal of Solid-State Circuits;2023-03
4. A 1.8GHz 12b Pre-Sampling Pipelined ADC with Reference Buffer and OP Power Relaxations;2023 IEEE International Solid- State Circuits Conference (ISSCC);2023-02-19
5. A 250 MS/s 65.8-dB SNDR SAR ADC With Cross-Phase Common-Mode Feedback and Reconfigurable Inverter-Based Preamplifier in 28-nm CMOS;IEEE Transactions on Circuits and Systems II: Express Briefs;2022-12
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