A PVT-Robust Open-loop Gm-Ratio ×16 Gain Residue Amplifier for >1 GS/s Pipelined ADCs-Reference-Cited by-同舟云学术

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A PVT-Robust Open-loop Gm-Ratio ×16 Gain Residue Amplifier for >1 GS/s Pipelined ADCs

Published:2024-05-19 Issue: Volume: Page:1-5
ISSN:
Container-title:2024 IEEE International Symposium on Circuits and Systems (ISCAS)
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Author:

Dias Diogo¹,Goes João¹,Costa Tiago²

Affiliation:

1. NOVA University of Lisbon,School of Science and Technology,Department of Electrical and Computers Engineering,Almada,Portugal

2. Delft University of Technology,Faculty of Electrical Eng., Mathematics and Computer Science,Department of Microelectronics,Delft,The Netherlands

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx8/10557746/10557828/10558154.pdf?arnumber=10558154

Reference13 articles.

1. A 12b 50MS/s 3.5mW SAR assisted 2-stage pipeline ADC

2. A 200MS/s, 11 bit SAR-assisted pipeline ADC with bias-enhanced ring amplifier

3. A 72-dB SNDR 130-MS/s 0.8-mW Pipelined-SAR ADC Using a Distributed Averaging Correlated Level Shifting Ring Amplifier

4. A 31.3fJ/conversion-step 70.4dB SNDR 30MS/s 1.2V two-step pipelined ADC in 0.13μm CMOS

5. 28.4 A 12b 330MS/s pipelined-SAR ADC with PVT-stabilized dynamic amplifier achieving <1dB SNDR variation

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