A 200MS/s, 11 bit SAR-assisted pipeline ADC with bias-enhanced ring amplifier

Author:

Chen Yongzhen,Wang Jingjing,Hu Hang,Ye Fan,Ren Junyan

Publisher

IEEE

Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A PVT-Robust Open-loop Gm-Ratio ×16 Gain Residue Amplifier for >1 GS/s Pipelined ADCs;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

2. Methods to Improve Linearity of Signal’s Analog-to-Digital Conversion with Self-Calibration;Machine Learning-based Design and Optimization of High-Speed Circuits;2023-12-31

3. High-Performance Floating Resistor-based Ring Amplifier for Switched Capacitor Circuits;2023 IEEE Nordic Circuits and Systems Conference (NorCAS);2023-10-31

4. VLSI Implementation of a High-Speed Pipeline A/D Converter;Role of 6G Wireless Networks in AI and Blockchain-Based Applications;2023-02-24

5. Design Techniques for Energy-Efficient Analog-to-Digital Converters;IEEE Open Journal of the Solid-State Circuits Society;2023

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