VLSI Implementation of a High-Speed Pipeline A/D Converter

Abstract

In very large-scale-integrated (VLSI) design, a challenge is to increase the speed without compromising the power consumption in an analog and mixed mode signal circuit. This research work is carried out to design a 12-bit pipeline A/D converter (ADC) of 400MS/s sampling rate to meet the high computing requirements. The design is focused to determine high speed and resolution in pipeline ADC to cater different applications. The main advantages of pipeline method are simple to implement, more flexible to improve the speed, and makes layout design simple. A proposed technique holds sample and hold circuit (S/H), multiplying DAC, comparator, and operational transconductance amplifier (OTA) to design the pipeline ADC architecture. OTA is used to convert differential input voltage into current with the help of a switched capacitor integrator module.