A 72-dB SNDR 130-MS/s 0.8-mW Pipelined-SAR ADC Using a Distributed Averaging Correlated Level Shifting Ring Amplifier-Reference-Cited by-同舟云学术

A 72-dB SNDR 130-MS/s 0.8-mW Pipelined-SAR ADC Using a Distributed Averaging Correlated Level Shifting Ring Amplifier

Published:2022-12 Issue:12 Volume:57 Page:3794-3803
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Wang Jia-Ching¹^ORCID,Kuo Tai-Haur¹^ORCID

Affiliation:

1. Department of Electrical Engineering, National Cheng Kung University (NCKU), Tainan, Taiwan

Funder

Ministry of Science and Technology (MOST) of Taiwan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/9962295/09866874.pdf?arnumber=9866874

Reference15 articles.

1. A 0.85 fJ/conversion-step 10b 200 kS/s subranging SAR ADC in 40 nm CMOS;tai;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2014

2. A 1.25-GS/s 7-b SAR ADC With 36.4-dB SNDR at 5 GHz Using Switch-Bootstrapping, USPC DAC and Triple-Tail Comparator in 28-nm CMOS

3. A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS

4. A 10 bit 320 MS/s Low-Cost SAR ADC for IEEE 802.11ac Applications in 20 nm CMOS

5. A 2.56 mW 40 MHz-bandwidth 75 dB-SNDR partial-interleaving SAR-assisted NS pipeline ADC with background inter-stage offset calibration;song;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2020

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