9.9 A 2.72fJ/conv 13b 2MS/s SAR ADC Using Dynamic Capacitive Comparator with Wide Input Common Mode
Author:
Affiliation:
1. Gwangju Institute of Science and Technology,Gwangju,Korea
Funder
National Research Foundation of Korea
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10454133/10454267/10454566.pdf?arnumber=10454566
Reference7 articles.
1. 26.2 A 5.5fJ/conv-step 6.4MS/S 13b SAR ADC utilizing a redundancy-facilitated background error-detection-and-correction scheme
2. 27.2 14.1-ENOB 184.9dB-FoM Capacitor-Array-Assisted Cascaded Charge-Injection SAR ADC
3. A 174μVRMS Input Noise, 1 GS/s Comparator in 22nm FDSOI with a Dynamic-Bias Preamplifier Using Tail Charge Pump and Capacitive Neutralization Across the Latch
4. An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier
5. A 0.82mW 14b 130MS/S Pipelined-SAR ADC With a Distributed Averaging Correlated Level Shifting (DACLS) Ringamp and Bypass-Window Backend
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