MemPool: A Scalable Manycore Architecture With a Low-Latency Shared L1 Memory
Author:
Affiliation:
1. Integrated Systems Laboratory (IIS), Swiss Federal Institute of Technology, Zurich, Switzerland
2. Independent Researcher, Zurich, Switzerland
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science,Software
Link
http://xplorestaging.ieee.org/ielx7/12/10311055/10227739.pdf?arnumber=10227739
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