In-Datacenter Performance Analysis of a Tensor Processing Unit-Reference-Cited by-同舟云学术

In-Datacenter Performance Analysis of a Tensor Processing Unit

Published:2017-06-24 Issue: Volume: Page:
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Container-title:Proceedings of the 44th Annual International Symposium on Computer Architecture
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Author:

Jouppi Norman P.¹,Young Cliff¹,Patil Nishant¹,Patterson David¹,Agrawal Gaurav¹,Bajwa Raminder¹,Bates Sarah¹,Bhatia Suresh¹,Boden Nan¹,Borchers Al¹,Boyle Rick¹,Cantin Pierre-luc¹,Chao Clifford¹,Clark Chris¹,Coriell Jeremy¹,Daley Mike¹,Dau Matt¹,Dean Jeffrey¹,Gelb Ben¹,Ghaemmaghami Tara Vazir¹,Gottipati Rajendra¹,Gulland William¹,Hagmann Robert¹,Ho C. Richard¹,Hogberg Doug¹,Hu John¹,Hundt Robert¹,Hurt Dan¹,Ibarz Julian¹,Jaffey Aaron¹,Jaworski Alek¹,Kaplan Alexander¹,Khaitan Harshit¹,Killebrew Daniel¹,Koch Andy¹,Kumar Naveen¹,Lacy Steve¹,Laudon James¹,Law James¹,Le Diemthu¹,Leary Chris¹,Liu Zhuyuan¹,Lucke Kyle¹,Lundin Alan¹,MacKean Gordon¹,Maggiore Adriana¹,Mahony Maire¹,Miller Kieran¹,Nagarajan Rahul¹,Narayanaswami Ravi¹,Ni Ray¹,Nix Kathy¹,Norrie Thomas¹,Omernick Mark¹,Penukonda Narayana¹,Phelps Andy¹,Ross Jonathan¹,Ross Matt¹,Salek Amir¹,Samadiani Emad¹,Severn Chris¹,Sizikov Gregory¹,Snelham Matthew¹,Souter Jed¹,Steinberg Dan¹,Swing Andy¹,Tan Mercedes¹,Thorson Gregory¹,Tian Bo¹,Toma Horia¹,Tuttle Erick¹,Vasudevan Vijay¹,Walter Richard¹,Wang Walter¹,Wilcox Eric¹,Yoon Doe Hyun¹

Affiliation:

1. Google, Inc., Mountain View, CA USA

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3079856.3080246

Reference61 articles.

1. Abadi M. Agarwal A. Barham P. Brevdo E. Chen Z. Citro C. Corrado G.S. Davis A. Dean J. Devin M. Ghemawat S. etal 2016. TensorFlow: Large-scale machine learning on heterogeneous distributed systems. arXiv:1603.04467. Abadi M. Agarwal A. Barham P. Brevdo E. Chen Z. Citro C. Corrado G.S. Davis A. Dean J. Devin M. Ghemawat S. et al. 2016. TensorFlow: Large-scale machine learning on heterogeneous distributed systems. arXiv:1603.04467.

2. Cnvlutin: Ineffectual-Neuron-Free Deep Neural Network Computing

3. Adolf R. Rama S. Reagen B. Wei G.Y. and Brooks D. 2016 September. Fathom: reference workloads for modern deep learning methods. IEEE Int'l Symp. on Workload Characterization (IISWC). Adolf R. Rama S. Reagen B. Wei G.Y. and Brooks D. 2016 September. Fathom: reference workloads for modern deep learning methods. IEEE Int'l Symp. on Workload Characterization (IISWC).

4. Asanović K. 2002. Programmable Neurocomputing in The Handbook of Brain Theory and Neural Networks: Second Edition M. A. Arbib (Ed.) MIT Press ISBN 0-262-01197-2 November 2002. Asanović K. 2002. Programmable Neurocomputing in The Handbook of Brain Theory and Neural Networks: Second Edition M. A. Arbib (Ed.) MIT Press ISBN 0-262-01197-2 November 2002.

5. Asanović K. 1998. Asanović K. Beck Johnson J. Wawrzynek J. Kingsbury B. and Morgan N. November 1998. Training Neural Networks with Spert-II. Chapter 11 in Parallel Architectures for Artificial Networks: Paradigms and Implementations N. Sundararajan and P. Saratchandran (Eds.) IEEE Computer Society Press ISBN 0-8186-8399-6. https://people.eecs.berkeley.edu/~krste/papers/annbook.pdf Asanović K. 1998. Asanović K. Beck Johnson J. Wawrzynek J. Kingsbury B. and Morgan N. November 1998. Training Neural Networks with Spert-II. Chapter 11 in Parallel Architectures for Artificial Networks: Paradigms and Implementations N. Sundararajan and P. Saratchandran (Eds.) IEEE Computer Society Press ISBN 0-8186-8399-6. https://people.eecs.berkeley.edu/~krste/papers/annbook.pdf

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