Accelerating ML Recommendation with over a Thousand RISC-V/Tensor Processors on Esperanto’s ET-SoC-1 Chip-Reference-Cited by-同舟云学术

Accelerating ML Recommendation with over a Thousand RISC-V/Tensor Processors on Esperanto’s ET-SoC-1 Chip

Published:2021-08-22 Issue: Volume: Page:
ISSN:
Container-title:2021 IEEE Hot Chips 33 Symposium (HCS)
language:
Short-container-title:

Author:

Ditzel Dave,Espasa Roger,Aymerich Nivard,Baum Allen,Berg Tom,Burr Jim,Hao Eric,Iyer Jayesh,Izquierdo Miquel,Jayaratnam Shankar,Jones Darren,Klingner Chris,Kim Jin,Lee Stephen,Lupon Marc,Magklis Grigorios,Maric Bojan,Nath Rajib,Neilly Mike,Northcutt Duane,Orner Bill,Renau Jose,Reves Gerard,Reves Xavier,Riordan Tom,Sanchez Pedro,Samudrala Sri,Sole Guillem,Tang Raymond,Thorn Tommy,Torres Francisco,Tortella Sebastia,Yau Daniel

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9566763/9566845/09566904.pdf?arnumber=9566904

Cited by 18 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Cycle-accurate multi-FPGA platform for accelerated emulation of large on-chip networks;The Journal of Supercomputing;2024-06-23

2. TeraPool-SDR: An 1.89TOPS 1024 RV-Cores 4MiB Shared-L1 Cluster for Next-Generation Open-Source Software-Defined Radios;Proceedings of the Great Lakes Symposium on VLSI 2024;2024-06-12

3. Virtual Coordinate System Based on a Circulant Topology for Routing in Networks-On-Chip;Symmetry;2024-01-21

4. MemPool: A Scalable Manycore Architecture With a Low-Latency Shared L1 Memory;IEEE Transactions on Computers;2023-12

5. FLEA - FIT-Aware Heuristic for Application Allocation in Many-Cores based on Q-Learning;2023 XIII Brazilian Symposium on Computing Systems Engineering (SBESC);2023-11-21