RC64: High performance rad-hard manycore
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/7494113/7500496/07500697.pdf?arnumber=7500697
Cited by 12 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Enabling Efficient Hybrid Systolic Computation in Shared-L1-Memory Manycore Clusters;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-09
2. A Parallel Architecture and Implementation for Near-Lossless Hyperspectral Image Compression Based on CCSDS 123.0-B-2 With Scalable Data-Rate Performance;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-09
3. MemPool: A Scalable Manycore Architecture With a Low-Latency Shared L1 Memory;IEEE Transactions on Computers;2023-12
4. Hybrid Modular Redundancy: Exploring Modular Redundancy Approaches in RISC-V Multi-Core Computing Clusters for Reliable Processing in Space;ACM Transactions on Cyber-Physical Systems;2023-11-30
5. Vision Based Lunar Landing Using RC64 Rad Hard DSP/ML Manycore Processor;2023 European Data Handling & Data Processing Conference (EDHPC);2023-10-02
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