Assembling 2-D Blocks Into 3-D Chips-Reference-Cited by-同舟云学术

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Assembling 2-D Blocks Into 3-D Chips

Published:2012-02 Issue:2 Volume:31 Page:228-241
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Knechtel Johann,Markov Igor L.,Lienig Jens

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx5/43/6132613/06132649.pdf?arnumber=6132649

Cited by 24 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Fast power density aware three‐dimensional integrated circuit floorplanning for hard macroblocks using best operator combination genetic algorithm;International Journal of Circuit Theory and Applications;2023-05-29

2. Hier-3D: A Methodology for Physical Hierarchy Exploration of 3D ICs;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023

3. Layoutmaßnahmen zur Verbesserung der Zuverlässigkeit;Grundlagen des Layoutentwurfs elektronischer Schaltungen;2023

4. Hier-3D: A Hierarchical Physical Design Methodology for Face-to-Face-Bonded 3D ICs;ACM/IEEE International Symposium on Low Power Electronics and Design;2022-08

5. Built-in Self-Test and Fault Localization for Inter-Layer Vias in Monolithic 3D ICs;ACM Journal on Emerging Technologies in Computing Systems;2022-01-31

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