Efficiency and Speed Trade-Offs in 8-Bit CMOS Adders at 180nm: An In-Depth Examination-Reference-Cited by-同舟云学术

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Efficiency and Speed Trade-Offs in 8-Bit CMOS Adders at 180nm: An In-Depth Examination

Published:2023-11-08 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE International Conference on Recent Advances in Systems Science and Engineering (RASSE)
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Author:

Ravindran Ajith¹,George Abraham¹,George Anish M¹,Cherian Deepthi²,Thomas Femi Elsa³,Kumar Sarath¹

Affiliation:

1. Saintgits College of Engineering,Department of Electronics Engineering,Kottayam,India

2. UST Global Information Technology Parks Pvt.Ltd,Trivandrum,India

3. Infosys Limited,Trivandrum,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10363431/10363424/10363562.pdf?arnumber=10363562

Reference105 articles.

1. A power efficient carry save adder and modified carry save adder using CMOS technology

2. Optimized low power full adder design

3. Analysis and comparative study of 8-bit adder for embedded application

4. Power-Delay-Product, Area and Threshold-Loss Analysis of CMOS Full Adder Circuits

5. A Systematic Delay and Power Dominant Carry Save Adder Design

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