Author:
Vamsi A Krishna,Kumar N Udaya,Sindhuri K Bala,Teja G Sai Chandra
Cited by
6 articles.
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1. Design of a 4-Bit 4-Operand Adder Using Verilog: An Abstraction Analysis;2024 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS);2024-02-24
2. A design method for the multi-operand adder in logic synthesis flow;2023 5th International Academic Exchange Conference on Science and Technology Innovation (IAECST);2023-12-08
3. Efficiency and Speed Trade-Offs in 8-Bit CMOS Adders at 180nm: An In-Depth Examination;2023 IEEE International Conference on Recent Advances in Systems Science and Engineering (RASSE);2023-11-08
4. Hybrid Brent Kung Adder with Modified Sum Generator for Energy Efficient Applications;Journal of Circuits, Systems and Computers;2023-03-06
5. Design of High-Speed 32-Bit Vedic Multiplier Using Verilog HDL;Lecture Notes in Electrical Engineering;2021-09-10