Design of High-Speed 32-Bit Vedic Multiplier Using Verilog HDL
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Springer Singapore
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https://link.springer.com/content/pdf/10.1007/978-981-16-3767-4_42
Reference15 articles.
1. Gupta T, Sharma JB (2018) A CSA-based architecture of vedic multiplier for complex multiplication. In: Perez G, Tiwari S, Trivedi M, Mishra K (eds) Ambient communications and computer systems. Advances in intelligent systems and computing, vol 696. Springer, Singapore. http://doi-org-443.webvpn.fjmu.edu.cn/https://doi.org/10.1007/978-981-10-7386-1_4
2. Jagannatha KB, Lakshmisagar HS, Bhaskar GR (2014) FPGA and ASIC implementation of 16-Bit vedic multiplier using Urdhva Triyakbhyam Sutra. In: Sridhar V, Sheshadri H, Padma M (eds) Emerging research in electronics, computer science and technology. Lecture notes in electrical engineering, vol 248. Springer, New Delhi. https://doi.org/10.1007/978-81-322-1157-0_4
3. Ram GC, Lakshmanna YR, Rani DS, Sindhuri KB (2016) Area efficient modified vedic multiplier In: 2016 international conference on circuit, power and computing technologies (ICCPCT), Nagercoil, pp 1–5. https://doi.org/10.1109/ICCPCT.2016.7530294
4. Gokhale GR, Gokhale SR (2015) Design of area and delay efficient Vedic multiplier using carry select adder. In: 2015 international conference on information processing (ICIP), Pune, pp 295–300. https://doi.org/10.1109/INFOP.2015.7489396
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