FPGA and ASIC Implementation of 16-Bit Vedic Multiplier Using Urdhva Triyakbhyam Sutra-Reference-Cited by-同舟云学术

FPGA and ASIC Implementation of 16-Bit Vedic Multiplier Using Urdhva Triyakbhyam Sutra

Published:2013-09-14 Issue: Volume: Page:31-38
ISSN:1876-1100
Container-title:Lecture Notes in Electrical Engineering
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Author:

Jagannatha K. B.,Lakshmisagar H. S.,Bhaskar G. R.

Publisher

Springer India

Link

http://link.springer.com/content/pdf/10.1007/978-81-322-1157-0_4

Reference7 articles.

1. Thesis by Amandeep Singh (2010) Implementation of 16 bit Vedic multiplier. Thapur University, Patiala. http://dspace.thapar.edu:8080/dspace/bitstream/10266/1109/4/1109.pdf

2. Dhillon HS, Mitra A (2008) A reduced-bit multiplication algorithm for digital arithmetics. Int J Comput Math Sci 2(2):64–69

3. Thapliyal H, Kotiyal S, Srinivas MB (2005) Design and analysis of a novel parallel square and cube architecture based on ancient Indian Vedic mathematics. In: Proceedings of IEEE centre for VLSI and embedded system technologies, International Institute of Information Technology, Hyderabad, India

4. Ramalatha M, Deena Dayalan K, Dharani P, Deborah Priya S (2009) High speed energy efficient ALU design using Vedic multiplication techniques. In Proceedings of IEEE international conference on advances in computational tools for engineering applications, 2009, ACTEA’09

5. Kumar A, Kumar D Siddhi hardware implementation of 16 × 16 bit multiplier and square using Vedic mathematics. Design Engineer, CDAC, Mohali

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