Author:
Jami Venkata Suman,Mani Anitha Priyadarshini Ganduluru,Mamidipaka Hema
Reference12 articles.
1. Y. D. Ykuntam, K. Pavani and K. Saladi, “Design and analysis of High Speed Wallace tree multiplier using Parallel prefix adders for VLSI circuit designs,” 11th International Conference on Computing, Communication and Networking Technologies, 1–6 (2020).
2. VLSI implementation of Wallace Tree Multiplier using Ladner-Fischer Adder
3. Implementation of Modified Booth-Wallace Tree Multiplier in FPGA
4. P. V. Krishna, K. Nirosha, G. Amala, N. Manikanta and Jami Venkata Suman, “Design and Implementation of FPGA based 32-bit Wallace and Systolic Multipliers,” International Journal of Creative Research Thoughts 6, 162–166 (2018).
5. ANN based SVC FACTS Controller to Enhance Voltage Stability of Multi-Machine Power System