A CSA-Based Architecture of Vedic Multiplier for Complex Multiplication

Author:

Gupta Tapsi,Sharma Janki Ballabh

Publisher

Springer Singapore

Reference8 articles.

1. K. D. Rao, Ch. Gngadhar, P. K. Korrai: FPGA implementation of complex multiplier using minimum delay Vedic real multiplier architecture. In: international conference on electrical, computer and electronics engineering (UPCON), pp. 580–584. IEEE, India (2016).

2. S. Sabeetha, J. Ajayan, S. Shriram, K. Vivek and V. Rajesh: A study of performance comparison of digital multipliers using 22 nm strained silicon technology. In: 2nd international conference on electronics and communication systems, pp. 180–184. IEEE, India (2015).

3. P. Mehta and D. Gawali: Conventional versus Vedic mathematical method for hardware implementation of multiplier. In: international conference on advances in computing, control and telecommunication technologies, pp. 640–642. IEEE, India (2009).

4. A. I. Sukowati, H. D. Putra and E. P. Wibowo: Usage area and speed performance analysis of Booth multiplier on its FPGA implementation. In: international conference on informatics and computing (ICIC), pp. 117–121. IEEE, Indonesia (2016).

5. G. C. Ram, D. S. Rani, R. Balasaikesava andK. B. Sindhuri: Design of delay efficient modified 16 bit wallace multiplier. In: international conference on recent trends in electronics, information and communication technology, pp. 1873–1877. IEEE, India (2016).

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1. ASIC Design and Implementation of a Power-Delay Product Optimized Arithmetic Operational Unit;2023 International Conference on Modeling, Simulation & Intelligent Computing (MoSICom);2023-12-07

2. Design of High-Speed 32-Bit Vedic Multiplier Using Verilog HDL;Lecture Notes in Electrical Engineering;2021-09-10

3. Han–Carlson adder based high-speed Vedic multiplier for complex multiplication;Microsystem Technologies;2018-04-06

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