Conventional versus Vedic Mathematical Method for Hardware Implementation of a Multiplier

Author:

Mehta Parth,Gawali Dhanashri

Publisher

IEEE

Cited by 29 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

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2. A novel reversible gate and optimised implementation of half adder, subtractor and 2-bit multiplier;Analog Integrated Circuits and Signal Processing;2023-12-24

3. Implementation of Efficient Vedic Multiplier and Its Performance Evaluation;Journal of Circuits, Systems and Computers;2023-09-07

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