Design of area and delay efficient Vedic multiplier using Carry Select Adder

Author:

Gokhale G. R.,Gokhale S. R.

Publisher

IEEE

Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. High efficient accurate DL-PO logic multiplier design for low power applications;AIP Conference Proceedings;2024

2. Design and implementation of 8 - bit multiplier using carry adder by comparing with carry look ahead;INTERNATIONAL CONFERENCE ON SCIENCE, ENGINEERING, AND TECHNOLOGY 2022: Conference Proceedings;2023

3. Design Of High-Speed Vedic Multiplier Using Urdhva Tiryakbhyam Sutra;2022 First International Conference on Electrical, Electronics, Information and Communication Technologies (ICEEICT);2022-02-16

4. Design of High-Speed 32-Bit Vedic Multiplier Using Verilog HDL;Lecture Notes in Electrical Engineering;2021-09-10

5. FPGA Implementation of 8-Bit Vedic Multiplier for DIT-FFT Application Using Urdhva Tiryagbhyam Sutra;International Journal of Advanced Research in Science, Communication and Technology;2021-02-10

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