Author:
Mahalakshmi R.,Sasilatha T.
Cited by
9 articles.
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1. Efficiency and Speed Trade-Offs in 8-Bit CMOS Adders at 180nm: An In-Depth Examination;2023 IEEE International Conference on Recent Advances in Systems Science and Engineering (RASSE);2023-11-08
2. FPGA Implementation of FIR Filter Using Quaternary Base Number System (QBNS);2023 International Conference on Electrical, Electronics, Communication and Computers (ELEXCOM);2023-08-26
3. FPGA Implementation of Efficient 32-Bit 3-Operand Addition Using Kogge–Stone (KS) Parallel Prefix Adder;Lecture Notes in Electrical Engineering;2023
4. Certain Investigations on Adder Design for VLSI Signal Processing;2022 8th International Conference on Advanced Computing and Communication Systems (ICACCS);2022-03-25
5. Design and Implementation of High-Speed Energy-Efficient Carry Select Adder for Image Processing Applications;Innovative Data Communication Technologies and Application;2022