FPGA Implementation of Efficient 32-Bit 3-Operand Addition Using Kogge–Stone (KS) Parallel Prefix Adder
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Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-19-7753-4_22
Reference15 articles.
1. Panda AK, Palisetty R, Ray KC (2020) High-speed area-efficient VLSI architecture of three-operand binary adder. IEEE Trans Circ Syst I Regul Pap 67(11):3944–3953. https://doi.org/10.1109/TCSI.2020.3016275
2. Mahalakshmi R, Sasilatha T (2013) A power efficient carry save adder and modified carry save adder using CMOS technology. In: 2013 IEEE international conference on computational intelligence and computing research, pp 1–5. https://doi.org/10.1109/ICCIC.2013.6724189
3. Daphni S, Vijula Grace KS (2021) Design an area efficient Kogge stone adder using pass transistor logic. In: 2021 Third international conference on intelligent communication technologies and virtual mobile networks (ICICV), pp 614–618. https://doi.org/10.1109/ICICV50876.2021.9388489
4. Padmanabhan TR, Bala Tripura Sundari B (2004) Introduction to Verilog. In: Design through Verilog HDL. IEEE, pp 11–29. https://doi.org/10.1002/0471723002.ch2
5. Panda AK, Ray KC (2020) A coupled variable input LCG method and its VLSI architecture for pseudorandom bit generation. In: IEEE transactions on instrumentation and measurement, vol 69, no 4, pp 1011–1019. https://doi.org/10.1109/TIM.2019.2909248
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