Analysis and comparative study of 8-bit adder for embedded application
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/7469254/7475237/07475290.pdf?arnumber=7475290
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. High-speed adder power reduction and speed improvement using modified kogee stone adder;AIP Conference Proceedings;2024
2. Design of Efficient Pipelined Parallel Prefix Lander Fischer Based on Carry Select Adder;Lecture Notes in Networks and Systems;2024
3. Efficiency and Speed Trade-Offs in 8-Bit CMOS Adders at 180nm: An In-Depth Examination;2023 IEEE International Conference on Recent Advances in Systems Science and Engineering (RASSE);2023-11-08
4. Denoising of ECG Signal Using Optimized IIR Filter Architecture—A CSD-Based Design;Advances in VLSI, Signal Processing, Power Electronics, IoT, Communication and Embedded Systems;2023-08-29
5. An area-optimized N-bit multiplication technique using N/2-bit multiplication algorithm;SN Applied Sciences;2019-10-08
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