High-speed adder power reduction and speed improvement using modified kogee stone adder

Author:

Yamala Sashi Reddy,Amudha V.

Publisher

AIP Publishing

Reference15 articles.

1. Kumar, B. C., and A. U. Kumar. 2017. “A 64-Bit M-Kogee Stone Carry Save Adder Is Designed for Reducing Area by Using Zero Finding Logic.” http://www.ijvdcs.org/uploads/361542IJVDCS13354-02.pdf.

2. Design of 32 bit Parallel Prefix Adders

3. Maroju SaiKumar, D. P. S. 2013. “Design and Performance Analysis of Various Adders Using Verilog.” International Journal of Computer Science and. https://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.695.3447&rep=rep1&type=pdf.

4. McCormick, Keith, and Jesus Salcedo. 2017. SPSS Statistics for Data Analysis and Visualization. John Wiley & Sons.

5. Assessment of various treatment modalities for isolated gingival recession defect- A retrospective study

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