Noise margin, critical charge and power-delay tradeoffs for SRAM design-Reference-Cited by-同舟云学术

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Noise margin, critical charge and power-delay tradeoffs for SRAM design

Published:2011-07 Issue: Volume: Page:
ISSN:
Container-title:2011 IEEE 17th International On-Line Testing Symposium
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Author:

Rajendran Aravind,Shiyanovskii Yuriy,Wolff Frank,Papachristou Chris

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/5979170/5993790/05993828.pdf?arnumber=5993828

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Detailed Electrical Analysis of SEE on 28 nm FDSOI SRAM Architectures;2023 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI);2023-08-28

2. Low-Power Dual-Vt 7T SRAM Bit-Cell With Reduced Area and Leakage;2022 IEEE Delhi Section Conference (DELCON);2022-02-11

3. Soft Errors Sensitivity of SRAM Cells in Hold, Write, Read and Half-Selected Conditions;Journal of Electronic Testing;2021-04

4. Soft Error Reliability of SRAM cells during the three operation states;2020 IEEE Latin-American Test Symposium (LATS);2020-03

5. Perspectives and challenges for organic thin film transistors: materials, devices, processes and applications;Journal of Materials Science: Materials in Electronics;2013-10-30

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