Low-Power Dual-Vt 7T SRAM Bit-Cell With Reduced Area and Leakage
Author:
Affiliation:
1. National Institute of Technology Tiruchirappalli,Department of Electronics and Communication Engineering,Tiruchirappalli,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9752769/9752688/09753131.pdf?arnumber=9753131
Reference20 articles.
1. Noise margin, critical charge and power-delay tradeoffs for SRAM design
2. Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies
3. Low-Power Cache Design Using 7T SRAM Cell
4. Stable SRAM cell design for the 32 nm node and beyond
5. A 250 mV 8 kb 40 nm Ultra-Low Power 9T Supply Feedback SRAM (SF-SRAM)
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1. A 7nm-Based Decodable Self-Resetting Regfile Circuit;2023 IEEE 15th International Conference on ASIC (ASICON);2023-10-24
2. Performance Evaluation of 9T and 6T SRAM Cells at 7nm Technology;2023 14th International Conference on Computing Communication and Networking Technologies (ICCCNT);2023-07-06
3. Dual Vt 7T SRAM Based In-Memory Compute Adder for Convolution Neural Network Applications;2023 2nd International Conference for Innovation in Technology (INOCON);2023-03-03
4. A 14 nm Single-Ended Schmitt Trigger SRAM Cell for Improved SNM & Delay;2022 IEEE International Symposium on Smart Electronic Systems (iSES);2022-12
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