Low-Power Dual-Vt 7T SRAM Bit-Cell With Reduced Area and Leakage

Author:

Yadav Sheethal1,Bansal Yash1,Joseph Biby1,Kavitha R. K.1

Affiliation:

1. National Institute of Technology Tiruchirappalli,Department of Electronics and Communication Engineering,Tiruchirappalli,India

Publisher

IEEE

Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A 7nm-Based Decodable Self-Resetting Regfile Circuit;2023 IEEE 15th International Conference on ASIC (ASICON);2023-10-24

2. Performance Evaluation of 9T and 6T SRAM Cells at 7nm Technology;2023 14th International Conference on Computing Communication and Networking Technologies (ICCCNT);2023-07-06

3. Dual Vt 7T SRAM Based In-Memory Compute Adder for Convolution Neural Network Applications;2023 2nd International Conference for Innovation in Technology (INOCON);2023-03-03

4. A 14 nm Single-Ended Schmitt Trigger SRAM Cell for Improved SNM & Delay;2022 IEEE International Symposium on Smart Electronic Systems (iSES);2022-12

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