Duty-cycle distortion and specifications for jitter test-signal generation

Author:

Marcu Mihai,Durbha Sriram,Gupta Sanjeev

Publisher

IEEE

Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A 50Gb/s PAM4 receiver with mid-frequency compensation and decision jitter cancellation;IEICE Electronics Express;2024-04-10

2. Signal Transmission Calibration Systems in Integrated Circuits;Machine Learning-based Design and Optimization of High-Speed Circuits;2023-12-31

3. Jitter generation model based on timing modulation and cross point calibration for jitter decomposition;Metrology and Measurement Systems;2023-07-26

4. An Improved Clock Cycle Measurement Method for High-Speed Serial Signal with Duty-Cycle-Distortion Jitter;2022 IEEE 5th International Conference on Computer and Communication Engineering Technology (CCET);2022-08-19

5. Minimum jitter‐based adaptive decision feedback equaliser for giga‐bit‐per‐second serial links;The Journal of Engineering;2015-01

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