A 50Gb/s PAM4 receiver with mid-frequency compensation and decision jitter cancellation-Reference-Cited by-同舟云学术

A 50Gb/s PAM4 receiver with mid-frequency compensation and decision jitter cancellation

Published:2024-04-10 Issue:7 Volume:21 Page:20240059-20240059
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Lv Yangyan¹,Xie Sheng¹,Qin Guoxuan¹,Mao Luhong²,Song Ruiliang³,Zhang Naibai³

Affiliation:

1. Tianjin Key Laboratory of Imaging and Sensing Micro-electronic Technology, School of Microelectronics, Tianjin University

2. School of Electrical and Information Engineering, Tianjin University

3. The 54th Research Institute, China Electronics Technology Group Corporation

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Link

https://www.jstage.jst.go.jp/article/elex/21/7/21_21.20240059/_pdf

Reference31 articles.

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2. [2] Y. Krupnik, et al.: “112-Gb/s PAM4 ADC-based SerDes receiver with resonant AFE for long-reach channels,” IEEE J. Solid-State Circuits 55 (2020) 1077 (DOI: 10.1109/JSSC.2019.2959511).

3. [3] N. Dikhaminjia, et al.: “PAM4 signaling considerations for high-speed serial links,” 2016 IEEE International Symposium on Electromagnetic Compatibility (EMC) (2016) 906 (DOI: 10.1109/ISEMC.2016.7571771).

4. [4] IEEE.P802.3bs/D3.5, “Draft standard for Ethernet amendment 10: media access control parameters, physical layers and management parameters for 200Gb/s and 400Gb/s operation,” (2017) http://www.ieee802.org/3/bs/

5. [5] Z. Li, et al.: “A 56-Gb/s PAM4 receiver analog front-end with fixed peaking frequency and bandwidth in 40-nm CMOS,” IEEE Trans. Circuits Syst. II, Exp. Briefs 68 (2021) 3058 (DOI: 10.1109/TCSII.2021.3074384).