An Improved Clock Cycle Measurement Method for High-Speed Serial Signal with Duty-Cycle-Distortion Jitter-Reference-Cited by-同舟云学术

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An Improved Clock Cycle Measurement Method for High-Speed Serial Signal with Duty-Cycle-Distortion Jitter

Published:2022-08-19 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE 5th International Conference on Computer and Communication Engineering Technology (CCET)
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Author:

Wu Tong¹,Song Kezhu¹,Zhao Hongwei¹

Affiliation:

1. University of Science and Technology of China,Department of Modern Physics,Hefei,China

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9906316/9906318/09906325.pdf?arnumber=9906325

Reference9 articles.

1. Clock Recovery Setup,0

2. A 0.32–2.7 Gb/s Reference-Less Continuous-Rate Clock and Data Recovery Circuit With Unrestricted and Fast Frequency Acquisition

3. A software PAM4 clock data recovery algorithm for high‐speed serial communication

4. Research and implementation of clock recovery method based on software PLL

5. Duty-cycle distortion and specifications for jitter test-signal generation

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