A configurable 2-in-1 SRAM compiler with constant-negative-level write driver for low Vmin in 16nm Fin-FET CMOS-Reference-Cited by-同舟云学术

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A configurable 2-in-1 SRAM compiler with constant-negative-level write driver for low Vmin in 16nm Fin-FET CMOS

Published:2014-11 Issue: Volume: Page:
ISSN:
Container-title:2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)
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Author:

Wu Ching-Wei,Chang Ming-Hung,Chen Chia-Cheng,Lee Robin,Liao Hung-Jen,Chang Jonathan

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/6996072/7008838/07008881.pdf?arnumber=7008881

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 3-nm FinFET 27.6-Mbit/mm² Single-Port 6T SRAM Enabling 0.48–1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking;IEEE Journal of Solid-State Circuits;2024-04

2. A 4.13-GHz UHS Pseudo Two-Port SRAM With BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4-nm FinFET Technology;IEEE Journal of Solid-State Circuits;2024-04

3. 15.3 A 3nm FinFET 4.3GHz 21.1Mb/mm2 Double-Pumping 1-Read and 1-Write Pseudo-2-Port SRAM with Folded-Bitline Multi-Bank Architecture;2024 IEEE International Solid-State Circuits Conference (ISSCC);2024-02-18

4. A 4.24-GHz 128×256 SRAM Operating Double Pump Read Write Same Cycle in 5-nm Technology;IEEE Solid-State Circuits Letters;2024

5. Design of Low Power and Energy Efficient Write Driver with Bitline Leakage Compensation for SRAM;Communications in Computer and Information Science;2024

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