15.3 A 3nm FinFET 4.3GHz 21.1Mb/mm2 Double-Pumping 1-Read and 1-Write Pseudo-2-Port SRAM with Folded-Bitline Multi-Bank Architecture
Author:
Affiliation:
1. TSMC Design Technology Japan,Yokohama,Japan
2. TSMC,Hsinchu,Taiwan
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10454133/10454267/10454463.pdf?arnumber=10454463
Reference6 articles.
1. A configurable 2-in-1 SRAM compiler with constant-negative-level write driver for low Vmin in 16nm Fin-FET CMOS
2. A 6.05-Mb/mm216-nm FinFET double pumping 1W1R 2-port SRAM with 313 ps read access time
3. A 4.24GHz 128X256 SRAM Operating Double Pump Read Write Same Cycle in 5nm Technology
4. A 4.0GHz UHS Pseudo Two-port SRAM with BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4nm FinFET Technology
5. A 5GHz 7nm L1 cache memory compiler for high-speed computing and mobile applications
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