A 4.24GHz 128X256 SRAM Operating Double Pump Read Write Same Cycle in 5nm Technology-Reference-Cited by-同舟云学术

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A 4.24GHz 128X256 SRAM Operating Double Pump Read Write Same Cycle in 5nm Technology

Published:2023-06-11 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
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Author:

Zhang Nick¹,Kim Young Suk¹,Hsu Peter¹,Kim Samsoo¹,Tao Derek¹,Liao Hung-Jen¹,Wang P.W.¹,Yeap Geoffrey¹,Li Quincy¹,Chang Tsung-Yung Jonathan¹

Affiliation:

1. Memory Solution Division (MSD), Taiwan Semiconductor Manufacturing Company,Taiwan

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10185199/10185158/10185268.pdf?arnumber=10185268

Reference7 articles.

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 4.13-GHz UHS Pseudo Two-Port SRAM With BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4-nm FinFET Technology;IEEE Journal of Solid-State Circuits;2024-04

2. 15.3 A 3nm FinFET 4.3GHz 21.1Mb/mm2 Double-Pumping 1-Read and 1-Write Pseudo-2-Port SRAM with Folded-Bitline Multi-Bank Architecture;2024 IEEE International Solid-State Circuits Conference (ISSCC);2024-02-18

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