A 4.13-GHz UHS Pseudo Two-Port SRAM With BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4-nm FinFET Technology-Reference-Cited by-同舟云学术

A 4.13-GHz UHS Pseudo Two-Port SRAM With BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4-nm FinFET Technology

Published:2024-04 Issue:4 Volume:59 Page:1216-1224
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Kim Jeongkyun¹^ORCID,Yook Byungho¹,Lee Youngo¹^ORCID,Choi Taemin¹,Choi Kyuwon¹,Lee Chanho¹,Lee Juchang¹,Kim Hyeongcheol¹,Yun Seok¹,Do Changhoon¹,Kwak Minwoo¹^ORCID,Kim Mijoung¹,Li Yunrong¹,Tang Hoyoung¹^ORCID,Kim Jaeyoung¹,Lee Inhak¹,Seo Dongwook¹,Baeck Sangyeop¹^ORCID

Affiliation:

1. Foundry Division, Samsung Electronics, Hwaseong, South Korea

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/4/10480871/10418238.pdf?arnumber=10418238

Reference12 articles.

1. 4nm Voltage Auto-Tracking SRAM Pulse Generator with Fully RC Optimized Row Auto-Tracking Write Assist Circuits

2. A 28nm 360ps-access-time two-port SRAM with a time-sharing scheme to circumvent read disturbs

3. Energy-Efficient High Bandwidth 6T SRAM Design on Intel 4 CMOS Technology

4. A configurable 2-in-1 SRAM compiler with constant-negative-level write driver for low Vmin in 16nm Fin-FET CMOS

5. 10T Differential-Signal SRAM Design in a 14-nm FinFET Technology for High-Speed Application

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