A 28nm 360ps-access-time two-port SRAM with a time-sharing scheme to circumvent read disturbs-Reference-Cited by-同舟云学术

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A 28nm 360ps-access-time two-port SRAM with a time-sharing scheme to circumvent read disturbs

Published:2012-02 Issue: Volume: Page:
ISSN:
Container-title:2012 IEEE International Solid-State Circuits Conference
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Author:

Ishii Yuichiro,Tsukamoto Yasumasa,Nii Koji,Fujiwara Hidehiro,Yabuuchi Makoto,Tanaka Koji,Tanaka Shinji,Shimazaki Yasuhisa

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/6171933/6176863/06176991.pdf?arnumber=6176991

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 4.13-GHz UHS Pseudo Two-Port SRAM With BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4-nm FinFET Technology;IEEE Journal of Solid-State Circuits;2024-04

2. Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology;Integration;2020-01

3. A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2018-11

4. Design of BiCMOS SRAMs for high‐speed SiGe applications;IET Circuits, Devices & Systems;2014-11

5. A 4R/2W Register File Design for UDVS Microprocessors in 65-nm CMOS;IEEE Transactions on Circuits and Systems II: Express Briefs;2012-12

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