A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Link
http://xplorestaging.ieee.org/ielx7/92/8502886/08463584.pdf?arnumber=8463584
Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Silicon cross-coupled gated tunneling diodes;Chip;2024-06
2. A 3-nm FinFET 27.6-Mbit/mm2 Single-Port 6T SRAM Enabling 0.48–1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking;IEEE Journal of Solid-State Circuits;2024-04
3. A Low-Power High-Speed Sensing Scheme for Single-Ended SRAM;IEICE Transactions on Electronics;2022-11-01
4. Disturbance Aware Dynamic Power Reduction in Synchronous 2RW Dual-Port 8T SRAM by Self-Adjusting Wordline Pulse Timing;IEEE Journal of Solid-State Circuits;2022
5. A Comprehensive Framework for Analysis of Time-Dependent Performance-Reliability Degradation of SRAM Cache Memory;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2021-05
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